/**
 * @file    gt9881_efc.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_EFC_H_
#define GT98XX_DEVICE_GT9881_EFC_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */
/**
 * @struct EfcTypedef
 * @brief EFC structure definition
 */
typedef struct tagEfcTypedef {
  __IO uint32_t CTL;              ///< Flash control register 
  __IO uint32_t CFG0;             ///< Flash configuration register0 
  __IO uint32_t CFG1;             ///< Flash configuration register1 
  __IO uint32_t CFG2;             ///< Flash configuration register2 
  __IO uint32_t CFG3;             ///< Flash configuration register3 
  __IO uint32_t CFG4;             ///< Flash configuration register4 
  __IO uint32_t CFG5;             ///< Flash configuration register5 
  __IO uint32_t CFG6;             ///< Flash configuration register6 
  __IO uint32_t CMD;              ///< Flash command register 
  __IO uint32_t LOCK;             ///< Flash access control register 
  __IO uint32_t STS0;             ///< Flash status register0 
  __IO uint32_t ERR_CLR;          ///< Flash error clear regiser 
  __IO uint32_t ERASE_CMD_KEY;    ///< Flash erase command key register 
  __IO uint32_t ERASE_ADDR;       ///< Flash erase address regisgter 
     uint32_t RESERVED0[6];       ///< Reserved 
  __IO uint32_t SEC_PROT0;        ///< Sector Protection Register0 
  __IO uint32_t SEC_PROT1;        ///< Sector Protection Register1 
  __IO uint32_t SEC_PROT2;        ///< Sector Protection Register2 
  __IO uint32_t SEC_PROT3;        ///< Sector Protection Register3 
  __IO uint32_t SEC_PROT4;        ///< Sector Protection Register4 
  __IO uint32_t SEC_PROT5;        ///< Sector Protection Register5 
  __IO uint32_t SEC_PROT6;        ///< Sector Protection Register6 
  __IO uint32_t SEC_PROT7;        ///< Sector Protection Register7 
  __IO uint32_t TRIM0;            ///< Trim data register 0 
  __IO uint32_t TRIM1;            ///< Trim data register 1 
  __IO uint32_t TRIM2;            ///< Trim data register 2 
  __IO uint32_t TRIM3;            ///< Trim data register 3 
  __IO uint32_t TRIM4;            ///< Trim data register 4 
  __IO uint32_t TRIM5;            ///< Trim data register 5 
  __IO uint32_t TRIM6;            ///< Trim data register 6 
  __IO uint32_t TRIM7;            ///< Trim data register 7 
  __IO uint32_t TRIM8;            ///< Trim data register 8 
  __IO uint32_t TRIM9;            ///< Trim data register 9 
} EfcTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define EFC_BASE               (PERIPH_BASE + 0x2000UL)    ///< EFC base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define EFC                ((EfcTypedef*)EFC_BASE)      ///< EFC operator
/** @} Peripheral_Declaration */



/**
 * @defgroup EFC_Bitmap EFC Bitmap
 * @ingroup Peripheral_Registers_Bits_Definition
 * @brief Bitmap of EFC Registers
 * @{
 */

#define EFC_CTL_CENVR_Pos                (0U)     ///< Position of EFC_CTL_CENVR
#define EFC_CTL_CENVR_Msk                (0x1UL << EFC_CTL_CENVR_Pos)    ///< Bitmask of EFC_CTL_CENVR
/**
 * @def     EFC_CTL_CENVR
 * @brief   Choose flash's main array or flash's NVR
 * <pre>
 * @a 1b'0 : Choose flash's main array
 * @a 1b'1 : Choose flash's NVR
 * Default value:1
 * </pre>
 */
#define EFC_CTL_CENVR                    EFC_CTL_CENVR_Msk

#define EFC_CTL_RETRY_Pos                (1U)     ///< Position of EFC_CTL_RETRY
#define EFC_CTL_RETRY_Msk                (0x1UL << EFC_CTL_RETRY_Pos)    ///< Bitmask of EFC_CTL_RETRY
/**
 * @def     EFC_CTL_RETRY
 * @brief   Enable/Disable retry operation
 * <pre>
 * @a 1b'0 : Disable
 * @a 1b'1 : Enable
 * </pre>
 */
#define EFC_CTL_RETRY                    EFC_CTL_RETRY_Msk

#define EFC_CFG0_TRW_Pos                 (0U)     ///< Position of EFC_CFG0_TRW
#define EFC_CFG0_TRW_Msk                 (0xFFUL << EFC_CFG0_TRW_Pos)    ///< Bitmask of EFC_CFG0_TRW
/**
 * @def     EFC_CFG0_TRW
 * @brief   Latency to next operation after program/erase.
 * <pre>
 * Default:8'd10
 * </pre>
 */
#define EFC_CFG0_TRW                     EFC_CFG0_TRW_Msk

#define EFC_CFG0_TRC_Pos                 (8U)     ///< Position of EFC_CFG0_TRC
#define EFC_CFG0_TRC_Msk                 (0xFFUL << EFC_CFG0_TRC_Pos)    ///< Bitmask of EFC_CFG0_TRC
/**
 * @def     EFC_CFG0_TRC
 * @brief   The access time or initial access time for read.
 * <pre>
 * Default:8'd3
 * </pre>
 */
#define EFC_CFG0_TRC                     EFC_CFG0_TRC_Msk

#define EFC_CFG0_TPROG_Pos               (16U)     ///< Position of EFC_CFG0_TPROG
#define EFC_CFG0_TPROG_Msk               (0xFFFFUL << EFC_CFG0_TPROG_Pos)    ///< Bitmask of EFC_CFG0_TPROG
/**
 * @def     EFC_CFG0_TPROG
 * @brief   The access time for physical write.
 * <pre>
 * Default:16'd700
 * </pre>
 */
#define EFC_CFG0_TPROG                   EFC_CFG0_TPROG_Msk

#define EFC_CFG1_SEC_Pos                 (0U)     ///< Position of EFC_CFG1_SEC
#define EFC_CFG1_SEC_Msk                 (0xFFFFFFFFUL << EFC_CFG1_SEC_Pos)    ///< Bitmask of EFC_CFG1_SEC
/**
 * @def     EFC_CFG1_SEC
 * @brief   Sector erase cycle. The erase time is (SEC) x Tclk_sys.
 * <pre>
 * Default:32'd450000.
 * </pre>
 */
#define EFC_CFG1_SEC                     EFC_CFG1_SEC_Msk

#define EFC_CFG2_CEC_Pos                 (0U)     ///< Position of EFC_CFG2_CEC
#define EFC_CFG2_CEC_Msk                 (0xFFFFFFFFUL << EFC_CFG2_CEC_Pos)    ///< Bitmask of EFC_CFG2_CEC
/**
 * @def     EFC_CFG2_CEC
 * @brief   Chip erase cycle. The erase time is (CEC)x Tclk_sys
 * <pre>
 * Default:32'd3000000
 * </pre>
 */
#define EFC_CFG2_CEC                     EFC_CFG2_CEC_Msk

#define EFC_CFG3_TPGS_Pos                (0U)     ///< Position of EFC_CFG3_TPGS
#define EFC_CFG3_TPGS_Msk                (0xFFFFUL << EFC_CFG3_TPGS_Pos)    ///< Bitmask of EFC_CFG3_TPGS
/**
 * @def     EFC_CFG3_TPGS
 * @brief   WEb low to PROG2 high Setup Time
 * <pre>
 * Default:16'd600
 * </pre>
 */
#define EFC_CFG3_TPGS                    EFC_CFG3_TPGS_Msk

#define EFC_CFG3_TPGH_Pos                (16U)     ///< Position of EFC_CFG3_TPGH
#define EFC_CFG3_TPGH_Msk                (0xFFFFUL << EFC_CFG3_TPGH_Pos)    ///< Bitmask of EFC_CFG3_TPGH
/**
 * @def     EFC_CFG3_TPGH
 * @brief   PROG2 Low to WEb high Hold time
 * <pre>
 * Default:16'd2
 * </pre>
 */
#define EFC_CFG3_TPGH                    EFC_CFG3_TPGH_Msk

#define EFC_CFG4_TNVS_Pos                (0U)     ///< Position of EFC_CFG4_TNVS
#define EFC_CFG4_TNVS_Msk                (0xFFFFUL << EFC_CFG4_TNVS_Pos)    ///< Bitmask of EFC_CFG4_TNVS
/**
 * @def     EFC_CFG4_TNVS
 * @brief   PROG/ERASE/CEb/NVR/Address to WEb Setup time
 * <pre>
 * Default:16'd1000
 * </pre>
 */
#define EFC_CFG4_TNVS                    EFC_CFG4_TNVS_Msk

#define EFC_CFG4_TRCV_PROG_Pos           (16U)     ///< Position of EFC_CFG4_TRCV_PROG
#define EFC_CFG4_TRCV_PROG_Msk           (0xFFFFUL << EFC_CFG4_TRCV_PROG_Pos)    ///< Bitmask of EFC_CFG4_TRCV_PROG
/**
 * @def   EFC_CFG4_TRCV_PROG
 * @brief Trcy_prog
 * @note Default : 16'd1000
 */
#define EFC_CFG4_TRCV_PROG                  EFC_CFG4_TRCV_PROG_Msk

#define EFC_CFG5_TRCV_ERASE_SECTOR_Pos      (0U)     ///< Position of EFC_CFG5_TRCV_ERASE_SECTOR
#define EFC_CFG5_TRCV_ERASE_SECTOR_Msk      (0xFFFFUL << EFC_CFG5_TRCV_ERASE_SECTOR_Pos)    ///< Bitmask of EFC_CFG5_TRCV_ERASE_SECTOR
/**
 * @def     EFC_CFG5_TRCV_ERASE_SECTOR
 * @brief   Sector erase recover time
 * <pre>
 * Default:16'd10000
 * </pre>
 */
#define EFC_CFG5_TRCV_ERASE_SECTOR          EFC_CFG5_TRCV_ERASE_SECTOR_Msk

#define EFC_CFG5_TRCV_ERASE_CHIP_Pos        (16U)     ///< Position of EFC_CFG5_TRCV_ERASE_CHIP
#define EFC_CFG5_TRCV_ERASE_CHIP_Msk        (0xFFFFUL << EFC_CFG5_TRCV_ERASE_CHIP_Pos)    ///< Bitmask of EFC_CFG5_TRCV_ERASE_CHIP
/**
 * @def     EFC_CFG5_TRCV_ERASE_CHIP
 * @brief   Chip erase recover time
 * <pre>
 * Default:16'd30000
 * </pre>
 */
#define EFC_CFG5_TRCV_ERASE_CHIP            EFC_CFG5_TRCV_ERASE_CHIP_Msk

#define EFC_CFG6_TWUP_Pos                   (0U)     ///< Position of EFC_CFG6_TWUP
#define EFC_CFG6_TWUP_Msk                   (0xFFFFUL << EFC_CFG6_TWUP_Pos)    ///< Bitmask of EFC_CFG6_TWUP
/**
 * @def     EFC_CFG6_TWUP
 * @brief   Wakeup time from deep stanby
 * <pre>
 * Default:16'd1000
 * </pre>
 */
#define EFC_CFG6_TWUP                       EFC_CFG6_TWUP_Msk

#define EFC_CMD_Pos                         (0U)     ///< Position of EFC_CMD
#define EFC_CMD_Msk                         (0x7FFUL << EFC_CMD_Pos)    ///< Bitmask of EFC_CMD
/**
 * @def     EFC_CMD
 * @brief   EFC control
 * <pre>
 * @a 3'h555 : Sector Erase
 * @a 3'hAAA : Chip Erase
 * @a 3'hA5A : Enter deep-standby status
 * @a 3'h5A5 : Exit deep-standby status
 * </pre>
 */
#define EFC_CMD                             EFC_CMD_Msk

#define EFC_LOCK_PRSP_Pos                   (0U)     ///< Position of EFC_LOCK_PRSP
#define EFC_LOCK_PRSP_Msk                   (0x1UL << EFC_LOCK_PRSP_Pos)    ///< Bitmask of EFC_LOCK_PRSP
/**
 * @def     EFC_LOCK_PRSP
 * @brief   parameter reg and sector protection
 * <pre>
 * @a 1b'0 : unlock
 * @a 1b'1 : lock
 * </pre>
 */
#define EFC_LOCK_PRSP                       EFC_LOCK_PRSP_Msk

#define EFC_LOCK_MAIN_ACC_Pos               (1U)     ///< Position of EFC_LOCK_MAIN_ACC
#define EFC_LOCK_MAIN_ACC_Msk               (0x1UL << EFC_LOCK_MAIN_ACC_Pos)    ///< Bitmask of EFC_LOCK_MAIN_ACC
/**
 * @def     EFC_LOCK_MAIN_ACC
 * @brief   Main array access
 * <pre>
 * @a 1b'0 : unlock
 * @a 1b'1 : lock
 * </pre>
 */
#define EFC_LOCK_MAIN_ACC                EFC_LOCK_MAIN_ACC_Msk

#define EFC_LOCK_NVR_ACC_Pos             (2U)     ///< Position of EFC_LOCK_NVR_ACC
#define EFC_LOCK_NVR_ACC_Msk             (0x1UL << EFC_LOCK_NVR_ACC_Pos)    ///< Bitmask of EFC_LOCK_NVR_ACC
/**
 * @def     EFC_LOCK_NVR_ACC
 * @brief   NVR access
 * <pre>
 * @a 1b'0 : unlock
 * @a 1b'1 : lock
 * </pre>
 */
#define EFC_LOCK_NVR_ACC                 EFC_LOCK_NVR_ACC_Msk

#define EFC_LOCK_EARSE_ACC_Pos           (3U)     ///< Position of EFC_LOCK_EARSE_ACC
#define EFC_LOCK_EARSE_ACC_Msk           (0x1UL << EFC_LOCK_EARSE_ACC_Pos)    ///< Bitmask of EFC_LOCK_EARSE_ACC
/**
 * @def     EFC_LOCK_EARSE_ACC
 * @brief   Earse access
 * <pre>
 * @a 1b'0 : unlock
 * @a 1b'1 : lock
 * </pre>
 */
#define EFC_LOCK_EARSE_ACC               EFC_LOCK_EARSE_ACC_Msk

#define EFC_STS0_OPST_Pos                (0U)     ///< Position of EFC_STS0_OPST
#define EFC_STS0_OPST_Msk                (0x1UL << EFC_STS0_OPST_Pos)    ///< Bitmask of EFC_STS0_OPST
/**
 * @def     EFC_STS0_OPST
 * @brief   Flash operation status.
 * <pre>
 * @a 1b'0 : The previous operation is not finish. Wait before further operation.
 * @a 1b'1 : The previous operation is finished. Further operation can be applied.
 * Default: 1
 * </pre>
 */
#define EFC_STS0_OPST                     EFC_STS0_OPST_Msk

#define EFC_STS0_BUSERR_Pos               (1U)     ///< Position of EFC_STS0_BUSERR
#define EFC_STS0_BUSERR_Msk               (0x1UL << EFC_STS0_BUSERR_Pos)    ///< Bitmask of EFC_STS0_BUSERR
/**
 * @def     EFC_STS0_BUSERR
 * @brief   Bus transfer error status flag
 * <pre>
 * @a 1b'0 : No error. (Default at reset)
 * @a 1b'1 : Bus transfer error
 * </pre>
 */
#define EFC_STS0_BUSERR                   EFC_STS0_BUSERR_Msk

#define EFC_STS0_REG_LOCK_Pos             (2U)     ///< Position of EFC_STS0_REG_LOCK
#define EFC_STS0_REG_LOCK_Msk             (0x1UL << EFC_STS0_REG_LOCK_Pos)    ///< Bitmask of EFC_STS0_REG_LOCK
/**
 * @def     EFC_STS0_REG_LOCK
 * @brief   Regigster access Lock.
 * <pre>
 * @a 1b'0 : EFC registers can be updated
 * @a 1b'1 : EFC registers cannnot be updated
 * </pre>
 */
#define EFC_STS0_REG_LOCK                 EFC_STS0_REG_LOCK_Msk

#define EFC_STS0_MAINARRAY_LOCK_Pos          (3U)     ///< Position of EFC_STS0_MAINARRAY_LOCK
#define EFC_STS0_MAINARRAY_LOCK_Msk          (0x1UL << EFC_STS0_MAINARRAY_LOCK_Pos)    ///< Bitmask of EFC_STS0_MAINARRAY_LOCK
/**
 * @def     EFC_STS0_MAINARRAY_LOCK
 * @brief   Main array write lock.
 * <pre>
 * @a 1b'0 : Main array can be updated
 * @a 1b'1 : Main array cannnot be updated
 * </pre>
 */
#define EFC_STS0_MAINARRAY_LOCK               EFC_STS0_MAINARRAY_LOCK_Msk

#define EFC_STS0_NVR_LOCK_Pos                 (4U)     ///< Position of EFC_STS0_NVR_LOCK
#define EFC_STS0_NVR_LOCK_Msk                 (0x1UL << EFC_STS0_NVR_LOCK_Pos)    ///< Bitmask of EFC_STS0_NVR_LOCK
/**
 * @def     EFC_STS0_NVR_LOCK
 * @brief   NVR write lock
 * <pre>
 * @a 1b'0 : NVR cannnot be updated
 * @a 1b'1 : NVR can be updated
 * </pre>
 */
#define EFC_STS0_NVR_LOCK                     EFC_STS0_NVR_LOCK_Msk

#define EFC_STS0_EARSE_LOCK_Pos          (5U)     ///< Position of EFC_STS0_EARSE_LOCK
#define EFC_STS0_EARSE_LOCK_Msk          (0x1UL << EFC_STS0_EARSE_LOCK_Pos)    ///< Bitmask of EFC_STS0_EARSE_LOCK
/**
 * @def     EFC_STS0_EARSE_LOCK
 * @brief   Erase lock.
 * <pre>
 * @a 1b'0 : Erase can be updated
 * @a 1b'1 : Erase cannnot be updated
 * </pre>
 */
#define EFC_STS0_EARSE_LOCK              EFC_STS0_EARSE_LOCK_Msk

#define EFC_STS0_INIT_STAT_Pos           (6U)     ///< Position of EFC_STS0_INIT_STAT
#define EFC_STS0_INIT_STAT_Msk           (0x1UL << EFC_STS0_INIT_STAT_Pos)    ///< Bitmask of EFC_STS0_INIT_STAT
/**
 * @def     EFC_STS0_INIT_STAT
 * @brief   Initialization status
 * <pre>
 * @a 1b'0 : Initialization not done
 * @a 1b'1 : Initialization done
 * </pre>
 */
#define EFC_STS0_INIT_STAT               EFC_STS0_INIT_STAT_Msk

#define EFC_STS0_UNAERR_Pos              (7U)     ///< Position of EFC_STS0_UNAERR
#define EFC_STS0_UNAERR_Msk              (0x1UL << EFC_STS0_UNAERR_Pos)    ///< Bitmask of EFC_STS0_UNAERR
/**
 * @def     EFC_STS0_UNAERR
 * @brief   Write address unalign error
 * <pre>
 * @a 1b'0 : There wasn't write address unalign error.
 * @a 1b'1 : There was write address unalign error.
 * </pre>
 */
#define EFC_STS0_UNAERR                  EFC_STS0_UNAERR_Msk

#define EFC_STS0_CURR_STAT_Pos           (8U)     ///< Position of EFC_STS0_CURR_STAT
#define EFC_STS0_CURR_STAT_Msk           (0xFUL << EFC_STS0_CURR_STAT_Pos)    ///< Bitmask of EFC_STS0_CURR_STAT
/**
 * @def     EFC_STS0_CURR_STAT
 * @brief   Reflection of FSM status
 * <pre>
 * @a 4'b0000 : IDLE
 * @a 4'b0001 : READ
 * @a 4'b0010 : PROGRAM
 * @a 4'b0011 : SECTOR_ERASE
 * @a 4'b0100 : CHIP_ERASE
 * @a 4'b0101 : ENTER_DPSTB
 * @a 4'b0110 : EXIT_DPSTB
 * </pre>
 */
#define EFC_STS0_CURR_STAT               EFC_STS0_CURR_STAT_Msk

#define EFC_ERR_CLR_BUSERR_CLR_Pos       (0U)     ///< Position of EFC_ERR_CLR_BUSERR_CLR
#define EFC_ERR_CLR_BUSERR_CLR_Msk       (0x1UL << EFC_ERR_CLR_BUSERR_CLR_Pos)    ///< Bitmask of EFC_ERR_CLR_BUSERR_CLR
/**
 * @def     EFC_ERR_CLR_BUSERR_CLR
 * @brief   Write 1 to this bit will clear STS.BUSERR and STS.UNAERR.
 */
#define EFC_ERR_CLR_BUSERR_CLR           EFC_ERR_CLR_BUSERR_CLR_Msk

#define EFC_ERASE_CMD_KEY_Pos            (0U)     ///< Position of EFC_ERASE_CMD_KEY
#define EFC_ERASE_CMD_KEY_Msk            (0xFFFFFFFFUL << EFC_ERASE_CMD_KEY_Pos)    ///< Bitmask of EFC_ERASE_CMD_KEY
/**
 * @def     EFC_ERASE_CMD_KEY
 * @brief   Write key to this register to enable corresponding sector erase
 * <pre>
 * @a 8'h50055005 :  Allow erase of main array
 * @a 8'h21591001 : Allow erase of Trim3 Sector
 * @a 8'h12531353 : Alllow erase of Trim2 Sector
 * @a 8'h41472603 : Allow erase of Trim1 Sector.
 * </pre>
 */
#define EFC_ERASE_CMD_KEY                EFC_ERASE_CMD_KEY_Msk

#define EFC_ERASE_ADDR_Pos               (0U)     ///< Position of EFC_ERASE_ADDR
#define EFC_ERASE_ADDR_Msk               (0xFFFFFFFFUL << EFC_ERASE_ADDR_Pos)    ///< Bitmask of EFC_ERASE_ADDR
/**
 * @def     EFC_ERASE_ADDR
 * @brief   Holding the address of sector to be erased
 */
#define EFC_ERASE_ADDR                   EFC_ERASE_ADDR_Msk

#define EFC_SEC_PROT0_Pos                (0U)     ///< Position of EFC_SEC_PROT0
#define EFC_SEC_PROT0_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT0_Pos)    ///< Bitmask of EFC_SEC_PROT0
/**
 * @def     EFC_SEC_PROT0
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 1~32
 * </pre>
 */
#define EFC_SEC_PROT0                    EFC_SEC_PROT0_Msk

#define EFC_SEC_PROT1_Pos                (0U)     ///< Position of EFC_SEC_PROT1
#define EFC_SEC_PROT1_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT1_Pos)    ///< Bitmask of EFC_SEC_PROT1
/**
 * @def     EFC_SEC_PROT1
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 33~64
 * </pre>
 */
#define EFC_SEC_PROT1                    EFC_SEC_PROT1_Msk

#define EFC_SEC_PROT2_Pos                (0U)     ///< Position of EFC_SEC_PROT2
#define EFC_SEC_PROT2_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT2_Pos)    ///< Bitmask of EFC_SEC_PROT2
/**
 * @def     EFC_SEC_PROT2
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 65~96
 * </pre>
 */
#define EFC_SEC_PROT2                    EFC_SEC_PROT2_Msk

#define EFC_SEC_PROT3_Pos                (0U)     ///< Position of EFC_SEC_PROT3
#define EFC_SEC_PROT3_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT3_Pos)    ///< Bitmask of EFC_SEC_PROT3
/**
 * @def     EFC_SEC_PROT3
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 97~128
 * </pre>
 */
#define EFC_SEC_PROT3                    EFC_SEC_PROT3_Msk

#define EFC_SEC_PROT4_Pos                (0U)     ///< Position of EFC_SEC_PROT4
#define EFC_SEC_PROT4_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT4_Pos)    ///< Bitmask of EFC_SEC_PROT4
/**
 * @def     EFC_SEC_PROT4
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 129~160
 * </pre>
 */
#define EFC_SEC_PROT4                    EFC_SEC_PROT4_Msk

#define EFC_SEC_PROT5_Pos                (0U)     ///< Position of EFC_SEC_PROT5
#define EFC_SEC_PROT5_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT5_Pos)    ///< Bitmask of EFC_SEC_PROT5
/**
 * @def     EFC_SEC_PROT5
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 161~192
 * </pre>
 */
#define EFC_SEC_PROT5                    EFC_SEC_PROT5_Msk

#define EFC_SEC_PROT6_Pos                (0U)     ///< Position of EFC_SEC_PROT6
#define EFC_SEC_PROT6_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT6_Pos)    ///< Bitmask of EFC_SEC_PROT6
/**
 * @def     EFC_SEC_PROT6
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 193~224
 * </pre>
 */
#define EFC_SEC_PROT6                    EFC_SEC_PROT6_Msk

#define EFC_SEC_PROT7_Pos                (0U)     ///< Position of EFC_SEC_PROT7
#define EFC_SEC_PROT7_Msk                (0xFFFFFFFFUL << EFC_SEC_PROT7_Pos)    ///< Bitmask of EFC_SEC_PROT7
/**
 * @def     EFC_SEC_PROT7
 * @brief   Main array section access disable.
 * <pre>
 * @a 1b'0 : Access enable
 * @a 1b'1 : Access disable
 * Bit 0~31 for sector 225~256
 * </pre>
 */
#define EFC_SEC_PROT7                    EFC_SEC_PROT7_Msk

#define EFC_TRMI0_Pos                   (0U)     ///< Position of EFC_TRMI0
#define EFC_TRMI0_Msk                   (0xFFFFFFFFUL << EFC_TRMI0_Pos)    ///< Bitmask of EFC_TRMI0
/**
 * @def     EFC_TRMI0
 * @brief   Trim data 0 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI0                       EFC_TRMI0_Msk

#define EFC_TRMI1_Pos                   (0U)     ///< Position of EFC_TRMI1
#define EFC_TRMI1_Msk                   (0xFFFFFFFFUL << EFC_TRMI1_Pos)    ///< Bitmask of EFC_TRMI1
/**
 * @def     EFC_TRMI1
 * @brief   Trim data 1 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI1                       EFC_TRMI1_Msk

#define EFC_TRMI2_Pos                   (0U)     ///< Position of EFC_TRMI2
#define EFC_TRMI2_Msk                   (0xFFFFFFFFUL << EFC_TRMI2_Pos)    ///< Bitmask of EFC_TRMI2
/**
 * @def     EFC_TRMI2
 * @brief   Trim data 2 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI2                       EFC_TRMI2_Msk

#define EFC_TRMI3_Pos                   (0U)     ///< Position of EFC_TRMI3
#define EFC_TRMI3_Msk                   (0xFFFFFFFFUL << EFC_TRMI3_Pos)    ///< Bitmask of EFC_TRMI3
/**
 * @def     EFC_TRMI3
 * @brief   Trim data 3 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI3                       EFC_TRMI3_Msk

#define EFC_TRMI4_Pos                   (0U)     ///< Position of EFC_TRMI4
#define EFC_TRMI4_Msk                   (0xFFFFFFFFUL << EFC_TRMI4_Pos)    ///< Bitmask of EFC_TRMI4
/**
 * @def     EFC_TRMI4
 * @brief   Trim data 4 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI4                       EFC_TRMI4_Msk

#define EFC_TRMI5_Pos                   (0U)     ///< Position of EFC_TRMI5
#define EFC_TRMI5_Msk                   (0xFFFFFFFFUL << EFC_TRMI5_Pos)    ///< Bitmask of EFC_TRMI5
/**
 * @def     EFC_TRMI5
 * @brief   Trim data 5 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI5                       EFC_TRMI5_Msk

#define EFC_TRMI6_Pos                   (0U)     ///< Position of EFC_TRMI6
#define EFC_TRMI6_Msk                   (0xFFFFFFFFUL << EFC_TRMI6_Pos)    ///< Bitmask of EFC_TRMI6
/**
 * @def     EFC_TRMI6
 * @brief   Trim data 6 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI6                       EFC_TRMI6_Msk

#define EFC_TRMI7_Pos                   (0U)     ///< Position of EFC_TRMI7
#define EFC_TRMI7_Msk                   (0xFFFFFFFFUL << EFC_TRMI7_Pos)    ///< Bitmask of EFC_TRMI7
/**
 * @def     EFC_TRMI7
 * @brief   Trim data 7 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI7                       EFC_TRMI7_Msk

#define EFC_TRMI8_Pos                   (0U)     ///< Position of EFC_TRMI8
#define EFC_TRMI8_Msk                   (0xFFFFFFFFUL << EFC_TRMI8_Pos)    ///< Bitmask of EFC_TRMI8
/**
 * @def     EFC_TRMI8
 * @brief   Trim data 8 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI8                       EFC_TRMI8_Msk

#define EFC_TRMI9_Pos                   (0U)     ///< Position of EFC_TRMI9
#define EFC_TRMI9_Msk                   (0xFFFFFFFFUL << EFC_TRMI9_Pos)    ///< Bitmask of EFC_TRMI9
/**
 * @def     EFC_TRMI9
 * @brief   Trim data 9 which load automatically from NVR after global reset.
 * <pre>
 * This register is not effected by remap reset)
 * </pre>
 */
#define EFC_TRMI9                       EFC_TRMI9_Msk

/** @} EFC_Bitmap */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def IS_EFC_INSTANCE
 * @brief Check if INSTANCE is EFC instance
 */
#define IS_EFC_INSTANCE(INSTANCE)         ((INSTANCE) == EFC)

/**
 * @enum EfcEraseCmdKey
 * @brief Write to EFC_ERASE_CMD_KEY to enable corresponding sector erase.
 */
typedef enum tagEfcEraseCmdKey {
  kEraseCmdKeyMainArray = 0x50055005,     ///< Allow erase of main array
  kEraseCmdKeyTrim3 = 0x21591001,         ///< Allow erase of Trim3 Sector
  kEraseCmdKeyTrim2 = 0x12531353,         ///< Allow erase of Trim2 Sector
  kEraseCmdKeyTrim1 = 0x41472603          ///< Allow erase of Trim1 Sector
} EfcEraseCmdKey;
/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __GT9881_EFC_H__ */


